Attiny13 Clock frequency and ADC

I am working with an Attiny13 AVR, which is programmed by arduino UNO over SPI.

I found a core for attiny13 and the content of the boards.txt file as follows;

#attiny13.name=Attiny13 @ 128 KHz (internal watchdog oscillator)

#attiny13.upload.using=arduino:arduinoisp
# attiny13.upload.protocol=avrispv2
# attiny2313at1.upload.using=pololu

#attiny13.upload.maximum_size=1024
#attiny13.upload.speed=250 # important for not losing connection to a slow processor

#attiny13.bootloader.low_fuses=0x7B
#attiny13.bootloader.high_fuses=0xFF

#attiny13.bootloader.unlock_bits=0x3F
#attiny13.bootloader.lock_bits=0x3F

#attiny13.build.mcu=attiny13
#attiny13.build.f_cpu=128000
#attiny13.build.core=core13
########################

attiny13e.name=Attiny 13A standalone 9.6Mhz
attiny13e.upload.using=arduino:arduinoisp
attiny13e.upload.maximum_size=1024
attiny13e.upload.speed=19200
attiny13e.maximum_data_size=64
attiny13e.bootloader.low_fuses=0x7A
attiny13e.bootloader.high_fuses=0xFF
attiny13e.bootloader.path=empty
attiny13e.bootloader.file=empty
attiny13e.bootloader.unlock_bits=0xFF
attiny13e.bootloader.lock_bits=0xFF
attiny13e.build.mcu=attiny13
attiny13e.upload.tool=avrdude
attiny13e.build.f_cpu=9600000L
attiny13e.build.core=core13

When I am programming the attiny13, I select the "Attiny 13A standalone 9.6Mhz" as target board.

So, I expect it to run at 9.6Mhz.

I set the TCCR0B register as follows to get "No prescaling"

TCCR0B |= _BV(CS00);
TCCR0B &= ~_BV(CS01);
TCCR0B &= ~_BV(CS02);

Also set the PWM mode as "Fast PWM" by changing the TCCR0A register.

TCCR0A |= _BV(WGM00);
TCCR0A |= _BV(WGM01);
TCCR0A &= ~_BV(WGM02);

With those settings I should get 9.6Mhz/256 = 37.5 Khz PWM frequency. However, when I connect the output of the PWM to a MOSFET for driving and LED strip, I get and audible buzzing from the MOSFET.

That prompt me to think that my clock is not running at 9.6Mhz, since 37.5Khz is not an audible frequency.

So, I did another quick search on the topic of clock frequency and found the following webpage;

https://www.avrprogrammers.com/howto/sysclk-prescaler

If I didnt get it wrong, this page says that my clock frequency is divided by 8 by default.

To be able to get no divisor, I need to reset all the bits.

I did so and reseted all the CLKPS bits.

CLKPR = (1<<CLKPCE);
CLKPR = (0<<CLKPS3) | (0<<CLKPS2) | (0<<CLKPS1) | (0<<CLKPS0);

So, in theory, I should get 9.6Mhz clock frequency with the divisor of 1.

When I use all those aforementioned settings, I no more hear a buzzing sound.

However, another problem emerged this time.

I use a potentiometer for controlling the brightness. When set the clock divisor to "1", behaviour of the potentiometer changed. Analog input does not read a value right away when I turned the potentiometer, so I need to turn it a little more to get the minimum brightness and it reaches to maximum brightness before I reach to other end of the potentiometer. So, I believe there is something wrong with the ADC.

Under the Analog to Digital Converter title I found the following information;

By default, the successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate.

So, my clock frequency is 9.6Mhz and I need to set a prescaler in between 9.6Mhz/20Khz= 48 and 9.6Mhz/50Khz = 192 for the ADCSRA register. I selected the division factor of 128, which requires setting all three bits ADPS2, ADPS1 and ADPS0.

ADCSRA != 1<< ADPS2;
ADCSRA != 1<< ADPS1;
ADCSRA != 1<< ADPS0;

This should set all three bits and keep the frequency of the ADC in between 50Khz - 200Khz.

However, I still get the same behaviour from the potentiometer.

Where am I wrong?

Answers


ADCSRA != 1<< ADPS2;
ADCSRA != 1<< ADPS1;
ADCSRA != 1<< ADPS0;

are three empty statements that have no effect. (They each retrun a boolean result.) Did you mean to write

ADCSRA |= 1<< ADPS2;
ADCSRA |= 1<< ADPS1;
ADCSRA |= 1<< ADPS0;

or

ADCSRA |= 1<< ADPS2 | 1<< ADPS1 | 1<< ADPS0;

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